1. Field of the Invention
The invention relates to methods of manufacturing a semiconductor device and a solid state image pickup device and, more particularly, to a method of manufacturing a semiconductor device and a solid state image pickup device using connecting exposure in which a desired pattern is divided into a plurality of patterns, the divided patterns are connected, and exposure is executed.
2. Related Background Art
In the case of forming a semiconductor device of a large chip size onto a semiconductor substrate, for example, a method of manufacturing the semiconductor device disclosed in U.S. Pat. No. 5,561,317, or the like, has been known.
FIGS. 13A to 13C are diagrams for explaining the manufacturing method of the semiconductor device disclosed in the U.S. patent referenced above.
FIG. 13A is a diagram showing a schematic pattern of a first layer on the semiconductor substrate. FIG. 13B is a diagram showing a schematic pattern of a first reticle which is used to form the first layer in FIG. 13A. FIG. 13C is a diagram showing a schematic pattern of a second reticle for forming a second layer.
Three patterns A, B, and C are divisionally provided in a first reticle 105. An IC pattern is formed in each pattern. The patterns A, B, and C are vertically arranged and connected and one chip is constructed by the connected patterns A, B, and C.
The first reticle 105 is set into a reduction projection type exposing apparatus. A layout of the first layer on a semiconductor substrate 101 (hereinafter, referred to as a wafer 101) is programmed in a manner such that the connected patterns shown in FIG. 13A are printed onto the wafer 101 by a system associated with the exposing apparatus. An alignment mark 103 shown in FIG. 13B is an alignment mark of a die-by-die system. As shown in FIG. 13A, after the patterns are exposed, the alignment marks 103 are formed on both sides of each of the connected patterns A, B, and C on the semiconductor substrate and become alignment marks (parent marks) 102 for the second layer.
When the first layer is printed, in the first reticle 105, by changing a position of a masking blade of the reduction projection type exposing apparatus every shot (pattern A, B, C), in the case of printing a portion of a pattern A, the portions of the patterns B and C are hidden by the blade, thereby preventing light from transmitting to the patterns B and C. When each of the patterns B and C is printed, processes are executed in a manner similar to those mentioned above.
After the patterns A, B, and C are formed, by executing ordinary semiconductor manufacturing processes such as etching, impurity diffusion, a CVD (Chemical Vapor Deposition) method, and the like, in accordance with the patterns, patterns in the second layer are formed.
Subsequently, in the second layer, a second reticle 106 shown in FIG. 13C is used and the alignment marks 102 serving as parent marks formed in the first layer are aligned so as to be matched with alignment marks 104 serving as child marks. That is, the alignment marks are aligned so that a pattern A′ lies on the pattern A and a pattern B′ lies on the pattern B. When patterns A′, B′, and C′ are exposed, they are exposed by changing the position of the masking blade in a manner similar to the first layer.
In the prior art, in the case wherein a wiring having an area which overlaps the connecting position is formed by using a connecting exposure technique such that the divided patterns are connected and exposed, the wiring which overlaps the connecting position is formed so as to have a margin which takes into consideration the alignment precision of the right and left shots with respect to the connecting position, as shown in FIG. 14. In FIG. 14, A denotes a width of wiring formed by the exposure using the reduction projecting apparatus for microminiature working; A′ a width of wiring formed by divisional exposure; and B a width of wiring formed by batch processing of exposure using the reduction projecting apparatus of a large exposure area. A′ is set to be larger than A in consideration of the margin in the connecting area. Although a method of changing the connecting position for every layer, for example, a method of changing the connecting position of the second layer to a position which perpendicularly crosses the connecting position of the first layer is also considered, there is a problem such that the apparatus and the processes become complicated.
However, in the semiconductor device and solid state image pickup device having a plurality of wiring layers, in which the wiring layer having the area which overlaps the connecting position and the wiring layer which does not have the area which overlaps the connecting position exist, if the patterns obtained by dividing the wiring layer having the area which overlaps the connecting position are connected and formed, since the patterns are formed in consideration of the alignment margin as mentioned above, there is a case where, in spite of the fact that the number of processing steps is increased and the reduction projecting apparatus for microminiature working is used, it is not advantageous in terms of the wiring width and a space between the wirings as compared with those in the case of forming the patterns by the batch processing of exposure by using the reduction projecting apparatus of the large exposure area.